#/****************************************************************************
#**  SCALASCA    http://www.scalasca.org/                                   **
#*****************************************************************************
#**  Copyright (c) 1998-2013                                                **
#**  Forschungszentrum Juelich GmbH, Juelich Supercomputing Centre          **
#**                                                                         **
#**  See the file COPYRIGHT in the package base directory for details       **
#****************************************************************************/

#### BlueGene/L-specific extract ####
#
# PAPI supports access to up to 52 counters at a time, however,
# Scalasca/KOJAK currently limit access to 28 at a time.
#
# UPC L3, PU0, PU1, TR & TS counters are per compute node.
# FPU ARITH & LDST counters are per core (FPU & 2NDFPU).
#
# A single measurement can contain:
# - one counter from each of FPU_ARITH 2NDFPU_ARITH FPU_LDST 2NDFPU_LDST
# - a selection from the rest (subject to certain conflicts)

# data access
compose DATA_ACCESS_L2$ = BGL_UPC_PU0_PREF_REQ_VALID + BGL_UPC_PU1_PREF_REQ_VALID
compose DATA_HIT_L2$ = BGL_UPC_PU0_PREF_STREAM_HIT + BGL_UPC_PU1_PREF_STREAM_HIT
measure DATA_HIT_L3$ = BGL_UPC_L3_CACHE_HIT
measure DATA_HIT_MEM = BGL_UPC_L3_CACHE_MISS_DATA_WILL_BE_REQED_DDR
compose DATA_LOAD_FROM_MEM = BGL_UPC_L3_MSHNDLR_TOOK_REQ_RDQ0 + BGL_UPC_L3_MSHNDLR_TOOK_REQ_RDQ1
measure DATA_STORE_INTO_MEM = BGL_UPC_L3_MSHNDLR_TOOK_REQ_WRBUF

aggroup BGL_CACHES = BGL_UPC_PU0_PREF_REQ_VALID BGL_UPC_PU1_PREF_REQ_VALID BGL_UPC_PU0_PREF_STREAM_HIT BGL_UPC_PU1_PREF_STREAM_HIT BGL_UPC_L3_CACHE_HIT BGL_UPC_L3_CACHE_MISS_DATA_WILL_BE_REQED_DDR BGL_UPC_L3_MSHNDLR_TOOK_REQ_RDQ0 BGL_UPC_L3_MSHNDLR_TOOK_REQ_RDQ1 BGL_UPC_L3_MSHNDLR_TOOK_REQ_WRBUF

# BGL_FPU_ARITH+BGL_FPU_LDST (only one set at a time)
aggroup BGL_FPU_A = BGL_FPU_ARITH_ADD_SUBTRACT BGL_FPU_LDST_DBL_LD BGL_2NDFPU_ARITH_OEDIPUS_OP BGL_2NDFPU_LDST_QUAD_LD
aggroup BGL_FPU_B = BGL_FPU_ARITH_MULT_DIV BGL_FPU_LDST_DBL_ST BGL_2NDFPU_ARITH_TRINARY_OP BGL_2NDFPU_LDST_QUAD_ST
aggroup BGL_FPU_C = BGL_2NDFPU_ARITH_ADD_SUBTRACT BGL_2NDFPU_LDST_DBL_LD BGL_FPU_ARITH_OEDIPUS_OP BGL_FPU_LDST_QUAD_LD
aggroup BGL_FPU_D = BGL_2NDFPU_ARITH_MULT_DIV BGL_2NDFPU_LDST_DBL_ST BGL_FPU_ARITH_TRINARY_OP BGL_FPU_LDST_QUAD_ST

aggroup BGL_FPU_ASDL = BGL_FPU_ARITH_ADD_SUBTRACT BGL_2NDFPU_ARITH_ADD_SUBTRACT BGL_FPU_LDST_DBL_LD BGL_2NDFPU_LDST_DBL_LD
aggroup BGL_FPU_MDDS = BGL_FPU_ARITH_MULT_DIV BGL_2NDFPU_ARITH_MULT_DIV BGL_FPU_LDST_DBL_ST BGL_2NDFPU_LDST_DBL_ST
aggroup BGL_FPU_OOQL = BGL_FPU_ARITH_OEDIPUS_OP BGL_2NDFPU_ARITH_OEDIPUS_OP BGL_FPU_LDST_QUAD_LD BGL_2NDFPU_LDST_QUAD_LD
aggroup BGL_FPU_TOQS = BGL_FPU_ARITH_TRINARY_OP BGL_2NDFPU_ARITH_TRINARY_OP BGL_FPU_LDST_QUAD_ST BGL_2NDFPU_LDST_QUAD_ST

# 35 BGL_UPC_L3 counters (conflicts with some combinations, therefore 2 groups)
aggroup BGL_UPC_L3_SOME = BGL_UPC_L3_CACHE_HIT BGL_UPC_L3_CACHE_MISS_DATA_ALRDY_WAY_DDR BGL_UPC_L3_CACHE_MISS_DATA_WILL_BE_REQED_DDR BGL_UPC_L3_EDRAM_ACCESS_CYCLE BGL_UPC_L3_EDRAM_RFR_CYCLE BGL_UPC_L3_LINE_STARTS_EVICT_LINE_NUM_PRESSURE BGL_UPC_L3_MISS_DIR_SET_DISBL BGL_UPC_L3_MISS_NO_WAY_SET_AVAIL BGL_UPC_L3_MISS_REQUIRING_CASTOUT BGL_UPC_L3_MISS_REQUIRING_REFILL_NO_WR_ALLOC BGL_UPC_L3_MSHNDLR_TOOK_REQ BGL_UPC_L3_MSHNDLR_TOOK_REQ_PLB_RDQ BGL_UPC_L3_MSHNDLR_TOOK_REQ_RDQ0 BGL_UPC_L3_MSHNDLR_TOOK_REQ_RDQ1 BGL_UPC_L3_MSHNDLR_TOOK_REQ_WRBUF BGL_UPC_L3_WRBUF_LINE_ALLOC BGL_UPC_L3_WRQ0_DEP_DBUF BGL_UPC_L3_WRQ0_DEP_DBUF_HIT
aggroup BGL_UPC_L3_CONT = BGL_UPC_L3_PAGE_CLOSE BGL_UPC_L3_PAGE_OPEN BGL_UPC_L3_PLB_WRQ_DEP_DBUF BGL_UPC_L3_PLB_WRQ_DEP_DBUF_HIT BGL_UPC_L3_PREF_REINS_PULL_OUT_NEXT_LINE BGL_UPC_L3_PREF_REQ_ACC_BY_PREF_UNIT BGL_UPC_L3_RD_BURST_1024B_LINE_RD BGL_UPC_L3_RD_EDR__ALL_KINDS_OF_RD BGL_UPC_L3_RD_MODIFY_WR_CYCLE_EDR BGL_UPC_L3_REQ_TKN_CACHE_INHIB_RD_REQ BGL_UPC_L3_REQ_TKN_CACHE_INHIB_WR BGL_UPC_L3_REQ_TKN_NEEDS_CASTOUT BGL_UPC_L3_REQ_TKN_NEEDS_REFILL BGL_UPC_L3_WRQ1_DEP_DBUF BGL_UPC_L3_WRQ1_DEP_DBUF_HIT BGL_UPC_L3_WR_EDRAM__INCLUDING_RMW

# 30 each BGL_UPC_PU0 & BGL_UPC_PU1 counters
aggroup BGL_UPC_PU0 = BGL_UPC_PU0_DCURD_WAIT_L3 BGL_UPC_PU0_DCURD_WAIT_LINK BGL_UPC_PU0_DCURD_WAIT_LOCK BGL_UPC_PU0_DCURD_WAIT_PLB BGL_UPC_PU0_DCURD_WAIT_SRAM BGL_UPC_PU0_DCURD_1_RD_PEND BGL_UPC_PU0_DCURD_2_RD_PEND BGL_UPC_PU0_DCURD_3_RD_PEND BGL_UPC_PU0_DCURD_BLIND_REQ BGL_UPC_PU0_DCURD_COHERENCY_STALL_WAR BGL_UPC_PU0_DCURD_L3_REQ BGL_UPC_PU0_DCURD_L3_REQ_PEND BGL_UPC_PU0_DCURD_LINK_REQ BGL_UPC_PU0_DCURD_LINK_REQ_PEND BGL_UPC_PU0_DCURD_LOCK_REQ BGL_UPC_PU0_DCURD_LOCK_REQ_PEND BGL_UPC_PU0_DCURD_PLB_REQ BGL_UPC_PU0_DCURD_RD_REQ BGL_UPC_PU0_DCURD_SRAM_REQ BGL_UPC_PU0_DCURD_SRAM_REQ_PEND BGL_UPC_PU0_PREF_FILTER_HIT BGL_UPC_PU0_PREF_PREF_PEND BGL_UPC_PU0_PREF_REQ_VALID BGL_UPC_PU0_PREF_SELF_HIT BGL_UPC_PU0_PREF_SNOOP_HIT_OTHER BGL_UPC_PU0_PREF_SNOOP_HIT_SAME BGL_UPC_PU0_PREF_STREAM_HIT
# (null) BGL_UPC_PU0_DCURD_PLB_REQ_PEND BGL_UPC_PU0_PREF_SNOOP_HIT_PLB
aggroup BGL_UPC_PU1 = BGL_UPC_PU1_DCURD_PLB_REQ BGL_UPC_PU1_DCURD_SRAM_REQ_PEND BGL_UPC_PU1_DCURD_WAIT_L3 BGL_UPC_PU1_DCURD_WAIT_LINK BGL_UPC_PU1_DCURD_WAIT_LOCK BGL_UPC_PU1_DCURD_WAIT_PLB BGL_UPC_PU1_DCURD_WAIT_SRAM BGL_UPC_PU1_DCURD_1_RD_PEND BGL_UPC_PU1_DCURD_2_RD_PEND BGL_UPC_PU1_DCURD_3_RD_PEND BGL_UPC_PU1_DCURD_BLIND_REQ BGL_UPC_PU1_DCURD_COHERENCY_STALL_WAR BGL_UPC_PU1_DCURD_L3_REQ BGL_UPC_PU1_DCURD_L3_REQ_PEND BGL_UPC_PU1_DCURD_LINK_REQ BGL_UPC_PU1_DCURD_LINK_REQ_PEND BGL_UPC_PU1_DCURD_LOCK_REQ BGL_UPC_PU1_DCURD_LOCK_REQ_PEND BGL_UPC_PU1_DCURD_RD_REQ BGL_UPC_PU1_DCURD_SRAM_REQ BGL_UPC_PU1_PREF_FILTER_HIT BGL_UPC_PU1_PREF_PREF_PEND BGL_UPC_PU1_PREF_REQ_VALID BGL_UPC_PU1_PREF_SELF_HIT BGL_UPC_PU1_PREF_SNOOP_HIT_OTHER BGL_UPC_PU1_PREF_SNOOP_HIT_SAME BGL_UPC_PU1_PREF_STREAM_HIT
# (null) BGL_UPC_PU1_DCURD_PLB_REQ_PEND BGL_UPC_PU1_PREF_SNOOP_HIT_PLB

aggroup BGL_NETWORKS = BGL_UPC_TR_SNDR_0_VC0_DPKTS_SENT BGL_UPC_TR_SNDR_0_VC1_DPKTS_SENT BGL_UPC_TR_SNDR_1_VC0_DPKTS_SENT BGL_UPC_TR_SNDR_1_VC1_DPKTS_SENT BGL_UPC_TR_SNDR_2_VC0_DPKTS_SENT BGL_UPC_TR_SNDR_2_VC1_DPKTS_SENT BGL_UPC_TR_RCV_0_VC0_FULL BGL_UPC_TR_RCV_0_VC1_FULL BGL_UPC_TR_RCV_1_VC0_FULL BGL_UPC_TR_RCV_1_VC1_FULL BGL_UPC_TR_RCV_2_VC0_FULL BGL_UPC_TR_RCV_2_VC1_FULL BGL_UPC_TS_XM_PKTS BGL_UPC_TS_XP_PKTS BGL_UPC_TS_YM_PKTS BGL_UPC_TS_YP_PKTS BGL_UPC_TS_ZM_PKTS BGL_UPC_TS_ZP_PKTS BGL_UPC_TS_XM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_XP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_YM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_YP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS

aggroup BGL_TORUS = BGL_UPC_TS_XM_PKTS BGL_UPC_TS_XP_PKTS BGL_UPC_TS_YM_PKTS BGL_UPC_TS_YP_PKTS BGL_UPC_TS_ZM_PKTS BGL_UPC_TS_ZP_PKTS BGL_UPC_TS_XM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_XP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_YM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_YP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS
compose BGL_TORUS_PKTS = BGL_UPC_TS_XM_PKTS + BGL_UPC_TS_XP_PKTS + BGL_UPC_TS_YM_PKTS + BGL_UPC_TS_YP_PKTS + BGL_UPC_TS_ZM_PKTS + BGL_UPC_TS_ZP_PKTS
compose BGL_TORUS_FULL = BGL_UPC_TS_XM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS + BGL_UPC_TS_XP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS + BGL_UPC_TS_YM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS + BGL_UPC_TS_YP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS + BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS + BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS

# BGL_UPC_TS network counters
aggroup BGL_TORUS_ALLX = BGL_UPC_TS_XM_32B_CHUNKS BGL_UPC_TS_XM_ACKS BGL_UPC_TS_XM_LINK_AVAIL_NO_VCBN_TOKENS BGL_UPC_TS_XM_LINK_AVAIL_NO_VCBP_TOKENS BGL_UPC_TS_XM_LINK_AVAIL_NO_VCD0_VCD1_TOKENS BGL_UPC_TS_XM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_XM_PKTS BGL_UPC_TS_XM_TOKEN_ACKS BGL_UPC_TS_XM_VCBN_CHUNKS BGL_UPC_TS_XM_VCBP_CHUNKS BGL_UPC_TS_XM_VCD0_CHUNKS BGL_UPC_TS_XM_VCD1_CHUNKS BGL_UPC_TS_XP_32B_CHUNKS BGL_UPC_TS_XP_ACKS BGL_UPC_TS_XP_LINK_AVAIL_NO_VCBN_TOKENS BGL_UPC_TS_XP_LINK_AVAIL_NO_VCBP_TOKENS BGL_UPC_TS_XP_LINK_AVAIL_NO_VCD0_VCD1_TOKENS BGL_UPC_TS_XP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_XP_PKTS BGL_UPC_TS_XP_TOKEN_ACKS BGL_UPC_TS_XP_VCBN_CHUNKS BGL_UPC_TS_XP_VCBP_CHUNKS BGL_UPC_TS_XP_VCD0_CHUNKS BGL_UPC_TS_XP_VCD1_CHUNKS
aggroup BGL_TORUS_ALLY = BGL_UPC_TS_YM_32B_CHUNKS BGL_UPC_TS_YM_ACKS BGL_UPC_TS_YM_LINK_AVAIL_NO_VCBN_TOKENS BGL_UPC_TS_YM_LINK_AVAIL_NO_VCBP_TOKENS BGL_UPC_TS_YM_LINK_AVAIL_NO_VCD0_VCD1_TOKENS BGL_UPC_TS_YM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_YM_PKTS BGL_UPC_TS_YM_TOKEN_ACKS BGL_UPC_TS_YM_VCBN_CHUNKS BGL_UPC_TS_YM_VCBP_CHUNKS BGL_UPC_TS_YM_VCD0_CHUNKS BGL_UPC_TS_YM_VCD1_CHUNKS BGL_UPC_TS_YP_32B_CHUNKS BGL_UPC_TS_YP_ACKS BGL_UPC_TS_YP_LINK_AVAIL_NO_VCBN_TOKENS BGL_UPC_TS_YP_LINK_AVAIL_NO_VCBP_TOKENS BGL_UPC_TS_YP_LINK_AVAIL_NO_VCD0_VCD1_TOKENS BGL_UPC_TS_YP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_YP_PKTS BGL_UPC_TS_YP_TOKEN_ACKS BGL_UPC_TS_YP_VCBN_CHUNKS BGL_UPC_TS_YP_VCBP_CHUNKS BGL_UPC_TS_YP_VCD0_CHUNKS BGL_UPC_TS_YP_VCD1_CHUNKS
aggroup BGL_TORUS_ALLZ = BGL_UPC_TS_ZM_32B_CHUNKS BGL_UPC_TS_ZM_ACKS BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCBN_TOKENS BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCBP_TOKENS BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCD0_VCD1_TOKENS BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_ZM_PKTS BGL_UPC_TS_ZM_TOKEN_ACKS BGL_UPC_TS_ZM_VCBN_CHUNKS BGL_UPC_TS_ZM_VCBP_CHUNKS BGL_UPC_TS_ZM_VCD0_CHUNKS BGL_UPC_TS_ZM_VCD1_CHUNKS BGL_UPC_TS_ZP_32B_CHUNKS BGL_UPC_TS_ZP_ACKS BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCBN_TOKENS BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCBP_TOKENS BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCD0_VCD1_TOKENS BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS BGL_UPC_TS_ZP_PKTS BGL_UPC_TS_ZP_TOKEN_ACKS BGL_UPC_TS_ZP_VCBN_CHUNKS BGL_UPC_TS_ZP_VCBP_CHUNKS BGL_UPC_TS_ZP_VCD0_CHUNKS BGL_UPC_TS_ZP_VCD1_CHUNKS

aggroup BGL_TREE = BGL_UPC_TR_SNDR_0_VC0_DPKTS_SENT BGL_UPC_TR_SNDR_0_VC1_DPKTS_SENT BGL_UPC_TR_SNDR_1_VC0_DPKTS_SENT BGL_UPC_TR_SNDR_1_VC1_DPKTS_SENT BGL_UPC_TR_SNDR_2_VC0_DPKTS_SENT BGL_UPC_TR_SNDR_2_VC1_DPKTS_SENT BGL_UPC_TR_RCV_0_VC0_FULL BGL_UPC_TR_RCV_0_VC1_FULL BGL_UPC_TR_RCV_1_VC0_FULL BGL_UPC_TR_RCV_1_VC1_FULL BGL_UPC_TR_RCV_2_VC0_FULL BGL_UPC_TR_RCV_2_VC1_FULL
compose BGL_TREE_PKTS = BGL_UPC_TR_SNDR_0_VC0_DPKTS_SENT + BGL_UPC_TR_SNDR_0_VC1_DPKTS_SENT + BGL_UPC_TR_SNDR_1_VC0_DPKTS_SENT + BGL_UPC_TR_SNDR_1_VC1_DPKTS_SENT + BGL_UPC_TR_SNDR_2_VC0_DPKTS_SENT + BGL_UPC_TR_SNDR_2_VC1_DPKTS_SENT
compose BGL_TREE_FULL = BGL_UPC_TR_RCV_0_VC0_FULL + BGL_UPC_TR_RCV_0_VC1_FULL + BGL_UPC_TR_RCV_1_VC0_FULL + BGL_UPC_TR_RCV_1_VC1_FULL + BGL_UPC_TR_RCV_2_VC0_FULL + BGL_UPC_TR_RCV_2_VC1_FULL

# BGL_UPC_TR network counters
aggroup BGL_TREE_SR_0 = BGL_UPC_TR_SNDR_0_VC0_EMPTY BGL_UPC_TR_SNDR_0_VC1_EMPTY BGL_UPC_TR_SNDR_0_VC0_CUT_THROUGH BGL_UPC_TR_SNDR_0_VC1_CUT_THROUGH BGL_UPC_TR_SNDR_0_VC0_PKT_SENT_TOTAL BGL_UPC_TR_SNDR_0_VC1_PKT_SENT_TOTAL BGL_UPC_TR_SNDR_0_VC0_DPKTS_SENT BGL_UPC_TR_SNDR_0_VC1_DPKTS_SENT BGL_UPC_TR_SNDR_0_IDLPKTS_SENT BGL_UPC_TR_SNDR_0_RESEND_ATTS BGL_UPC_TR_SNDR_0_SRAM_ERR_CORR BGL_UPC_TR_RCV_0_VC0_DPKT_RCV BGL_UPC_TR_RCV_0_VC1_DPKT_RCV BGL_UPC_TR_RCV_0_VC0_EMPTY_PKT BGL_UPC_TR_RCV_0_VC1_EMPTY_PKT BGL_UPC_TR_RCV_0_IDLPKT BGL_UPC_TR_RCV_0_KNOWN_BAD_PKT_MARKER BGL_UPC_TR_RCV_0_VC0_CUT_THROUGH BGL_UPC_TR_RCV_0_VC1_CUT_THROUGH BGL_UPC_TR_RCV_0_VC0_FULL BGL_UPC_TR_RCV_0_VC1_FULL BGL_UPC_TR_RCV_0_HDR_PARITY_ERR BGL_UPC_TR_RCV_0_CRC_ERR BGL_UPC_TR_RCV_0_UNEXPCT_HDR_ERR BGL_UPC_TR_RCV_0_SRAM_ERR_CORR
aggroup BGL_TREE_SR_1 = BGL_UPC_TR_SNDR_1_VC1_DPKTS_SENT BGL_UPC_TR_RCV_1_HDR_PARITY_ERR BGL_UPC_TR_RCV_1_VC0_DPKT_RCV BGL_UPC_TR_RCV_1_VC1_DPKT_RCV BGL_UPC_TR_SNDR_1_VC0_EMPTY BGL_UPC_TR_SNDR_1_VC0_DPKTS_SENT BGL_UPC_TR_SNDR_1_VC0_PKT_SENT_TOTAL BGL_UPC_TR_RCV_1_VC0_EMPTY_PKT BGL_UPC_TR_RCV_1_VC1_EMPTY_PKT BGL_UPC_TR_RCV_1_IDLPKT BGL_UPC_TR_RCV_1_KNOWN_BAD_PKT_MARKER BGL_UPC_TR_RCV_1_VC0_CUT_THROUGH BGL_UPC_TR_RCV_1_VC1_CUT_THROUGH BGL_UPC_TR_RCV_1_VC0_FULL BGL_UPC_TR_RCV_1_VC1_FULL BGL_UPC_TR_RCV_1_CRC_ERR BGL_UPC_TR_RCV_1_UNEXPCT_HDR_ERR BGL_UPC_TR_RCV_1_SRAM_ERR_CORR BGL_UPC_TR_SNDR_1_VC1_EMPTY BGL_UPC_TR_SNDR_1_VC0_CUT_THROUGH BGL_UPC_TR_SNDR_1_VC1_CUT_THROUGH BGL_UPC_TR_SNDR_1_VC1_PKT_SENT_TOTAL BGL_UPC_TR_SNDR_1_IDLPKTS_SENT BGL_UPC_TR_SNDR_1_RESEND_ATTS BGL_UPC_TR_SNDR_1_SRAM_ERR_CORR
aggroup BGL_TREE_SR_2 = BGL_UPC_TR_SNDR_2_VC1_PKT_SENT_TOTAL BGL_UPC_TR_SNDR_2_VC1_DPKTS_SENT BGL_UPC_TR_RCV_2_VC1_CUT_THROUGH BGL_UPC_TR_RCV_2_VC1_FULL BGL_UPC_TR_SNDR_2_IDLPKTS_SENT BGL_UPC_TR_RCV_2_HDR_PARITY_ERR BGL_UPC_TR_SNDR_2_VC0_EMPTY BGL_UPC_TR_SNDR_2_VC0_CUT_THROUGH BGL_UPC_TR_SNDR_2_VC0_PKT_SENT_TOTAL BGL_UPC_TR_SNDR_2_VC0_DPKTS_SENT BGL_UPC_TR_SNDR_2_RESEND_ATTS BGL_UPC_TR_SNDR_2_SRAM_ERR_CORR BGL_UPC_TR_RCV_2_VC0_DPKT_RCV BGL_UPC_TR_RCV_2_VC0_EMPTY_PKT BGL_UPC_TR_RCV_2_IDLPKT BGL_UPC_TR_RCV_2_KNOWN_BAD_PKT_MARKER BGL_UPC_TR_RCV_2_VC0_CUT_THROUGH BGL_UPC_TR_RCV_2_VC0_FULL BGL_UPC_TR_RCV_2_CRC_ERR BGL_UPC_TR_RCV_2_UNEXPCT_HDR_ERR BGL_UPC_TR_RCV_2_SRAM_ERR_CORR BGL_UPC_TR_SNDR_2_VC1_EMPTY BGL_UPC_TR_SNDR_2_VC1_CUT_THROUGH BGL_UPC_TR_RCV_2_VC1_DPKT_RCV BGL_UPC_TR_RCV_2_VC1_EMPTY_PKT
# BGL_UPC_TR_RCV_[012]_RESYNCH_MODE_AFTER_ERR apparently not configurable
