#/****************************************************************************
#**  SCALASCA    http://www.scalasca.org/                                   **
#*****************************************************************************
#**  Copyright (c) 1998-2013                                                **
#**  Forschungszentrum Juelich GmbH, Juelich Supercomputing Centre          **
#**                                                                         **
#**  See the file COPYRIGHT in the package base directory for details       **
#****************************************************************************/

#### BlueGene/Q-specific extract ####
#
# Scalasca/KOJAK currently limit access to 28 counters at a time,
# however, hardware limitations for particular components may limit the number of
# valid counters to 6, 12 or 24 according to the number of hardware threads used.
#
# Components: 
# * PUnit::: "processor A2core/Opcode/L1p/Wakeup events" (thread or core scope)
# * L2Unit::: "chip level-2 cache events" (node-shared scope)
# * IOUnit::: "input/output events" (node-shared scope)
# * NWUnit::: "network link events" (exclusive scope)
# * CNKUnit::: "compute node kernel events" (node scope)
#
# Counters from different components have different overheads,
# which aggregate when multiple components are used simultaneously.

# BGPM event tips (A2 CPU core cycles breakdown)
aggroup BGQ_CYCLES = PEVT_CYCLES PEVT_XU_TIMEBASE_TICK PEVT_IU_TOT_ISSUE_COUNT PEVT_IU_IS1_STALL_CYC PEVT_IU_AXU_FXU_DEP_HIT_CYC PEVT_IU_AXU_DEP_HIT_CYC

aggroup BGQ_CYCLES_1 = PEVT_IU_IS1_STALL_CYC PEVT_IU_IS2_STALL_CYC PEVT_IU_AXU_FXU_DEP_HIT_CYC PEVT_IU_AXU_DEP_HIT_CYC
aggroup BGQ_CYCLES_2 = PEVT_IU_AXU_FXU_DEP_HIT_CYC PEVT_IU_AXU_DEP_HIT_CYC PEVT_IU_RAW_DEP_HIT_CYC PEVT_IU_WAW_DEP_HIT_CYC 
aggroup BGQ_CYCLES_3 = PEVT_IU_AXU_FXU_DEP_HIT_CYC PEVT_IU_SYNC_DEP_HIT_CYC PEVT_IU_SPR_DEP_HIT_CYC PEVT_IU_BARRIER_OP_STALL_CYC
aggroup BGQ_CYCLES_4 = PEVT_IU_AXU_FXU_DEP_HIT_CYC PEVT_XU_STALLED_ON_WAITRSV_CYC PEVT_IU_SLOW_SPR_ACCESS_CYC PEVT_IU_SPR_DEP_HIT_CYC

# HPM groups
# a good basic set, can count 1-4 threads/core
aggroup BGQ_HPM0 = PEVT_LSU_COMMIT_LD_MISSES PEVT_LSU_COMMIT_CACHEABLE_LDS PEVT_L1P_BAS_MISS PEVT_INST_XU_ALL PEVT_INST_QFPU_ALL PEVT_INST_QFPU_FPGRP1
# counters for load/stores, can count 1-2 threads/core
aggroup BGQ_HPM1 = PEVT_LSU_COMMIT_LD_MISSES PEVT_L1P_BAS_HIT PEVT_L1P_BAS_MISS PEVT_L1P_BAS_LD PEVT_INST_XU_LD PEVT_INST_XU_ST PEVT_INST_XU_FLD PEVT_INST_XU_FST PEVT_INST_XU_QLD PEVT_INST_XU_QST PEVT_INST_XU_ALL PEVT_INST_ALL
# all FPU counters, can count only 1 thread/core
aggroup BGQ_HPM2 = PEVT_INST_ALL PEVT_INST_QFPU_ALL PEVT_INST_QFPU_FOTH PEVT_INST_QFPU_FRES PEVT_INST_QFPU_FADD PEVT_INST_QFPU_FCVT PEVT_INST_QFPU_FCMP PEVT_INST_QFPU_FDIV PEVT_INST_QFPU_FMOV PEVT_INST_QFPU_FMA PEVT_INST_QFPU_FMUL PEVT_INST_QFPU_FRND PEVT_INST_QFPU_FSQE PEVT_INST_QFPU_FSQ PEVT_INST_QFPU_QMOV PEVT_INST_QFPU_QOTH PEVT_INST_QFPU_QADD PEVT_INST_QFPU_QMUL PEVT_INST_QFPU_QRES PEVT_INST_QFPU_QMA PEVT_INST_QFPU_QRND PEVT_INST_QFPU_QCVT PEVT_INST_QFPU_QCMP PEVT_INST_QFPU_FPGRP1
# normal pipe FPU instructions, can count 1-2 threads/core
aggroup BGQ_HPM3 = PEVT_INST_QFPU_FOTH PEVT_INST_QFPU_FRES PEVT_INST_QFPU_FADD PEVT_INST_QFPU_FCVT PEVT_INST_QFPU_FCMP PEVT_INST_QFPU_FDIV PEVT_INST_QFPU_FMOV PEVT_INST_QFPU_FMA PEVT_INST_QFPU_FMUL PEVT_INST_QFPU_FRND PEVT_INST_QFPU_FSQE PEVT_INST_QFPU_FSQ
# normal pipe FPU instructions, can count 1-4 threads/core
aggroup BGQ_HPM30 = PEVT_INST_QFPU_FOTH PEVT_INST_QFPU_FRES PEVT_INST_QFPU_FADD PEVT_INST_QFPU_FCVT PEVT_INST_QFPU_FCMP PEVT_INST_QFPU_FDIV
aggroup BGQ_HPM31 = PEVT_INST_QFPU_FMOV PEVT_INST_QFPU_FMA PEVT_INST_QFPU_FMUL PEVT_INST_QFPU_FRND PEVT_INST_QFPU_FSQE PEVT_INST_QFPU_FSQ
# qpx FPU instructions, can count 1-2 threads/core
aggroup BGQ_HPM4 = PEVT_INST_ALL PEVT_INST_QFPU_ALL PEVT_INST_QFPU_QMOV PEVT_INST_QFPU_QOTH PEVT_INST_QFPU_QADD PEVT_INST_QFPU_QMUL PEVT_INST_QFPU_QRES PEVT_INST_QFPU_QMA PEVT_INST_QFPU_QRND PEVT_INST_QFPU_QCVT PEVT_INST_QFPU_QCMP PEVT_INST_QFPU_FPGRP1
# qpx FPU instructions, can count 1-4 threads/core
aggroup BGQ_HPM40 = PEVT_INST_ALL PEVT_INST_QFPU_ALL PEVT_INST_QFPU_QMOV PEVT_INST_QFPU_QOTH PEVT_INST_QFPU_QADD PEVT_INST_QFPU_QMUL
aggroup BGQ_HPM41 = PEVT_INST_QFPU_QRES PEVT_INST_QFPU_QMA PEVT_INST_QFPU_QRND PEVT_INST_QFPU_QCVT PEVT_INST_QFPU_QCMP PEVT_INST_QFPU_FPGRP1
# all FXU counters, can count only 1 thread/core
aggroup BGQ_HPM5 = PEVT_INST_XU_FLD PEVT_INST_XU_FST PEVT_INST_XU_QLD PEVT_INST_XU_QST PEVT_INST_XU_BITS PEVT_INST_XU_BRC PEVT_INST_XU_BRU PEVT_INST_XU_CINV PEVT_INST_XU_CSTO PEVT_INST_XU_CTCH PEVT_INST_XU_IADD PEVT_INST_XU_ICMP PEVT_INST_XU_IDIV PEVT_INST_XU_ILOG PEVT_INST_XU_IMOV PEVT_INST_XU_IMUL PEVT_INST_XU_INT PEVT_INST_XU_LD PEVT_INST_XU_ST PEVT_INST_XU_LSCX PEVT_INST_XU_SYNC PEVT_INST_XU_TLB PEVT_INST_XU_TLBI PEVT_INST_XU_ALL

# last level cache miss rate and memory bandwidth (node-shared)
aggroup BGQ_LLC = L2Unit:::PEVT_L2_HITS L2Unit:::PEVT_L2_MISSES L2Unit:::PEVT_L2_FETCH_LINE L2Unit:::PEVT_L2_STORE_LINE

# all counters from IOUnit (node-shared)
aggroup BGQ_IO = PEVT_MU_PKT_INJ PEVT_MU_MSG_INJ PEVT_MU_FIFO_PKT_RCV PEVT_MU_RGET_PKT_RCV PEVT_MU_PUT_PKT_RCV PEVT_MU_PORT0_16B_WRT PEVT_MU_PORT0_32B_RD PEVT_MU_PORT0_64B_RD PEVT_MU_PORT0_128B_RD PEVT_MU_PORT1_16B_WRT PEVT_MU_PORT1_32B_RD PEVT_MU_PORT1_64B_RD PEVT_MU_PORT1_128B_RD PEVT_MU_PORT2_16B_WRT PEVT_MU_PORT2_32B_RD PEVT_MU_PORT2_64B_RD PEVT_MU_PORT2_128B_RD PEVT_MU_SLV_PORT_RD PEVT_MU_SLV_PORT_WRT PEVT_MU_PORT0_PEND_WRT PEVT_MU_PORT0_PEND_RD PEVT_MU_PORT1_PEND_WRT PEVT_MU_PORT1_PEND_RD PEVT_MU_PORT2_PEND_WRT PEVT_MU_PORT2_PEND_RD

# group suggested by Bob Walkup
aggroup BGQ_BW = PEVT_LSU_COMMIT_CACHEABLE_LDS PEVT_L1P_BAS_MISS PEVT_INST_XU_ALL PEVT_INST_QFPU_ALL PEVT_INST_QFPU_FPGRP1 PEVT_L2_HITS PEVT_L2_MISSES PEVT_L2_FETCH_LINE PEVT_L2_STORE_LINE PEVT_CNKHWT_SYSCALL
